This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to fabrication of integrated circuits (ICs) including silicon controlled rectifiers (SCRs), also referred to as thyristors.
ICs, including complementary metal-oxide-semiconductor (CMOS) devices, are susceptible to undesired parasitic SCR action known as latchup, which if not controlled can lead to damage to the IC. Latchup describes a type of short circuit that occurs due to the existence within the CMOS circuit of parasitic SCR structures. The parasitic SCR structures comprise PNPN junctions which act as a PNP transistor and an NPN transistor cross coupled to each other. Under certain conditions, such as the presence of a transient signal, one of the PN junctions can be forward biased, which turns on the SCR. The device can remain turned on in a latchup state even after the signal which causes the forward biasing on the PN junction is removed. The two transistors keep each other in saturation for as long as the SCR structure is forward-biased. Reduction of latchup effects is important for improved functioning of ICs.
While some SCRs in an IC may comprise latchup SCRs as described above, other SCRs may be included in an IC to dissipate electrostatic discharge (ESD) events. An ESD event refers to an electrical discharge of a current (positive or negative) for a short duration, during which a large amount of current is provided to the CMOS device. The large current may be built up from a variety of sources, for example, the human body. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) of a short duration (typically, 100 nanoseconds). An ESD event may be generated by human contact with the leads of an IC of by electrically charged machinery being discharged in other leads of an IC. Such ESD events may destroy an IC if not dissipated safely. An ESD event may be dissipated by an ESD SCR that sustains high currents, holding the voltage across the SCR at a low level. Therefore, ESD SCRs may be included in an IC to bypass high currents associated with an ESD event.